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| SiI 2022 Fibre Channel SerDes Silicon Image's SiI 2022 serializer/deserializer (SerDes) is capable of transmitting and receiving data at 1.0625 and 2.125 gigabits-per-second (Gbps). Targeted at Fibre Channel applications, the SiI 2022 SerDes is designed for power, performance and price. Making use of a robust, CMOS design that significantly reduces power dissipation and jitter, the SiI 2022 provides a low-cost solution for applications that require a high-performance Fibre Channel SerDes. Available in a 64-pin, 14x14 mm MQFP package, the SiI 2022 supports selectable transmit and receive data rates for automatic speed negotiation and a narrow 10-bit SSTL_2-compatible interface for parallel data input/output. The SiI 2022 SerDes leverages much of the circuit innovation at the physical layer of Silicon Image's proprietary reduced overhead Multi-layer Serial Link (MSLTM) architecture, pioneered and proven through the company's market-leading PanelLink(R) products. MSL technology is a multi-layer approach to providing robust, cost-effective, multi-gigabit semiconductor solutions on a single chip for high-bandwidth applications. Fibre Channel Applications * Host Bus Adapters * Hubs and Switches * Disk Drives * RAID Systems * High-Speed Backplanes Fibre Channel t Tape Backup Unit Fibre Channel Fibre Channel Server Server SiI 2022 Fibre Channel SerDes SiI 2022 Tx[0:9] Tx+ Input Latch Serializer Tx- 1.0625/2.125 Gbps transmit signal Tx_RATE TBC Tx PLL Loop-back REFCLK[0:1] Rx PLL RBC_SYNC Rx_RATE RBC[0:1] SiI 2022 Features Fibre Channel SerDes Rx[0:9] Data Output Byte Sync Deserializer Rx+ Sampler Rx- 1.0625/2.125 Gbps receive signal COM_DET EN_CDET * Fibre Channel-compliant * Multi-rate: 1.0625 Gbps and 2.125 Gbps Low Power * Single 3.3V supply for core circuits and high-speed I/O * Power dissipation: 450 mW Highly Reliable Serial Interface Cost Effective * Standard CMOS technology * Compact 64-pin, 14x14mm MQFP (Metric Quad Flat Pack) Narrow Parallel I/O Interface * Separately selectable Tx and Rx data rates * Very-low-jitter PLL: 3.3 ps (random jitter), 32 ps (deterministic jitter) * Variable pre-emphasis control * Variable on-chip termination resistor * Full ESD tolerance to 2 kV * MSLTM-based technology proven with PanelLink(R) ICs for the PC and CE markets (2-5 Gbps, over 30M units shipped) * Robust design for "noisy" environments * 10-bit interface with DDR for 2.125 Gbps mode * SSTL_2 and High-Speed Parallel Interface (HSPI)-compliant * Separate transmit byte clock (TBC) for latching parallel input data Proven Technology Part Number - SII2022CM64 Silicon Image, Inc. 1060 E. Arques, Sunnyvale, CA 94085 T 408.616.4000 F 408.830.9530 www.siliconimage.com (c)2002 Silicon Image, Inc. All rights reserved. Silicon Image, the Silicon Image logo, MSL, SiI, SiI 2022, SiI 2023, and PanelLink are trademarks or registered trademarks of Silicon Image, Inc. in the United States and other countries. Product specifications are subject to change without notice. Printed in the U.S.A. 6/02 SiI-PB-0028 EWRAP Rx_LOS General |
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